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    Proving the correctness of the interlock mechanism in processor design. 

    Li, Xiaoshan; Cau, A. (Antonio); Moszkowski, B. C.; Coleman, Nick; Zedan, Hussein (Chapman & Hall on behalf of the International Federation for Information Processing (IFIP), 1997)
    In this paper, Interval Temporal Logic (ITL) us used to specify and verify the event processor EP/3, which is a multi-threaded pipeline processor capable of executing parallel programs. We first give the high level ...
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    Author
    Cau, A. (Antonio) (1)
    Coleman, Nick (1)Li, Xiaoshan (1)Moszkowski, B. C. (1)
    Zedan, Hussein (1)
    Subjectcompositionality (1)
    executable specification (1)
    interval temporal logic (1)processor verification (1)... View MoreDate Issued1997 (1)Has File(s)Yes (1)

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